1. Field of the Invention
The present invention relates to delta-sigma modulators in general, and in particular to delta-sigma modulators that are constructed from a basic building block of a first order low-pass filter.
2. Description of the Related Art
Delta-sigma modulators are widely used in over-sampling analog to digital converters (ADC) to achieve high-resolution analog-to-digital data conversion despite using coarse quantization. Delta-sigma modulators can be either discrete-time, which use discrete-time loop filters, or continuous-time, which use continuous-time loop filters.
In a typical discrete-time delta-sigma modulator, a sample and hold amplifier converts a continuous-time analog input signal into discrete-time analog samples. A discrete-time loop filter H(z) filters the discrete-time analog sample and inputs the filtered discrete-time analog sample into a quantizer. The quantizer output is fed back via a digital-to-analog converter (DAC) and subtracted from the input sample by a summing circuit.
The discrete-time loop filter H(z) is constructed using one or more discrete-time integrators, which are designed to mimic or approximate the ideal response of k/(z−1), where k is a gain constant. A switch-capacitor circuit is typically used to implement the discrete-time integrator. Functionally, a switch-capacitor integrator comprises a capacitor CS for sampling the input, a capacitor CI for integrating the input, and an operational trans-impedance amplifier (OTA), where the output voltage of the OTA is proportional to the charge stored on CI. The output discrete-time voltage is an integration of the input discrete-time voltage.
One problem with prior art discrete-time delta-sigma modulators is that there is inevitably some leakage for the charge stored on the integrating capacitor CI due to finite output resistance of the OTA. Instead of exhibiting an ideal response of k/(z−1), a practical discrete-time integrator exhibits a response of k/(z−α), where α<1 is a leakage factor depending on the value of CI and the output resistance of the OTA. To ensure the leakage is small, i.e. α is close to 1 (mathematically, 1−α<<1, a large integrating capacitor CI, an OTA with high output resistance, or a combination of both is used. In practice, large devices, which consume high power, are typically used. The problem becomes more pronounced for high-speed delta-sigma modulators based on low voltage, deep sub-micron CMOS processes. In such processes, it is typically difficult to design a high-speed OTA with high output resistance.
In a typical continuous-time delta-sigma modulator, a continuous-time loop filter H(s) filters the continuous-time input signal and a quantizer converts the filtered analog signal into a discrete time output sample in accordance with a clock signal. The quantizer output is fed back via a digital-to-analog converter (DAC) and subtracted from the input signal by a summing circuit.
The continuous-time loop filter H(s) is typically constructed using one or more continuous-time integrators, which are designed to mimic the ideal response of k/s, where k is a gain constant. For high-speed applications, a trans-impedance amplifier-capacitor (OTA-C) circuit comprising an operational trans-impedance amplifier (OTA) and a capacitor C is typically used to implement the continuous-time integrator. In the typical operation of an OTA-C integrator with a transconductance of Gm, the OTA converts the input voltage into a current, which is integrated by the capacitor C at the output. The OTA output voltage is proportional to the time-integral of the input voltage.
In practice, the finite output resistance of the OTA results in a leakage and causes the integrator to exhibit a response of k/(s+p), where p is a pole determined by the output resistance of the OTA and the capacitor C. To ensure the leakage is small, i.e. p is very small compared to the clock frequency (mathematically, p<<2π/T where T is the clock period), a large integrating capacitor, an OTA with high output resistance, or a combination of both is used. In practice, large devices, which typically consume high power, are used. The problem becomes more pronounced for high-speed delta-sigma modulators based on low voltage, deep sub-micron CMOS processes, because in such processes it is typically difficult to design high-speed OTA with a high output resistance.